Virage Logic Corporation (Virage Logic) has introduced new Intelli DDR3 System Aware IP and Intelli LPDDR2 low-power memory interface IP. The new Intelli DDR3 System Aware IP solution is system validated at speeds more than 1.6 Gigabits-per-second (Gb/s) on a 65nm process, for high-performance applications. The Intelli DDR3 memory interface is a complete end-to-end solution including a DRAM memory controller, I/O and the new all-digital PHY+DLL.

The new Intelli LPDDR2 low-power memory interface IP is designed to meet the latest draft of the JEDEC LPDDR2 specification. The high-efficiency Intelli LPDDR2 solution is designed to offer optimal performance at the power and area needed for a wide range of high-performance portable devices, allowing video, graphics and other applications that consumer’s desire.

The company has made a strategic investment in developing the low-power IP solutions with scalable architectures to offer the basis for the new electronic devices. The Intelli LPDDR product line is designed to efficiently meet the stringent demands of customers’ current low-power applications like digital video IP cores from Imagination Technologies with built-in flexibility to adapt as requirements evolve.

As a leading IP provider ourselves, Imagination Technologies values our relationship with fellow IP vendors particularly highly, said Tony King-Smith, vice president of marketing, Imagination Technologies. Virage Logic is a long-standing trusted IP partner for Imagination, supplying us with innovative memory solutions that provide tangible higher data throughput efficiency, portability and performance benefits. We license our System-on-Chip (SoC) IP cores and platforms to a wide range of top semiconductor and consumer electronics companies around the world, and integrating Intelli LPDDR into some of our products helps us stay at the forefront of the industry. Virage Logic’s all-digital architecture helps Imagination to create advanced SoC IP solutions that deliver lower system costs and power usage, with the highest confidence for first time silicon success.

The System Aware IP Intelli DDR product line features a new digital architecture and system intelligence to help manage variables inherent in high speed interface designs, accelerating implementation and optimizing integration with existing board and package designs. The company’s solution also allows application-specific designs to attain faster time-to-market; higher data throughput efficiency, decreased system costs and less power consumption, and creates high confidence in first-time silicon success.

We selected Virage Logic’s Intelli DDR for our recently launched SiI6100 LiquidHD(TM) display processor as it enables higher data-throughput efficiency for the multi-format audio/video decoder on the SoC, said Michael Buechel, senior manager, Office of Program Management at Silicon Image, Inc.

The new Intelli DDR3 System Aware IP is a complete end-to-end solution that extends beyond the chip level. Building on its Silicon Aware IP that addresses impact of advanced process behavior on SoC devices, the company architected its Intelli DDR3 solution to manage the impact of environment on system behavior and performance, spanning SoC core-to-interface, interface-to-package, and package-to-board. This approach results in higher performance solution at considerably lower risk and cost.

As the semiconductor industry’s trusted IP partner, leading companies that develop SoCs for set top boxes, digital video recorders, printers, mobile handheld devices and many other consumer electronics products look to us to provide reliable DDR interface solutions that will meet their power, performance, and data bandwidth requirements, said Luigi Ternullo, senior product marketing manager, Virage Logic. With the system-validated Intelli DDR3 and the new Intelli LPDDR2, our broad product line provides low-risk solutions ideally suited for both high-performance and low-power applications.

Availability of the company’s Intelli Product Line:

The company’s system-validated Intelli DDR3 1.6 Gb/s product is available on a 65nm process and a preliminary test chip report is available by request for the qualified customers. The new Intelli DDR3 will also be available later this quarter on the 40/45nm process. The new Intelli LPDDR2 is being provided for early adopters on 65nm and 40/45nm LP processes, with general availability planned for 2010.

The company will showcase its new Intelli product line, along with its full semiconductor IP portfolio, at DesignCon 2009 Conference at the Santa Clara Convention Center, Booth #301, on February 3 and February 4, 2009. The company will feature a live demo of its 1.6 Gb/s Intelli DDR3 memory system running on a SoC and using the Intelli DDR2/3 controller and Intelli DDR2/3 PHY+DLL and I/O.

About the company’s Silicon Aware IP and System Aware IP Solutions:

To help the SoC designers address complex predictability and manufacturability challenges at advanced process nodes, in 2005 the company pioneered a new class of semiconductor IP called Silicon Aware IP. The company’s Silicon Aware IP offering (embedded memories and logic libraries) incorporates silicon behavior knowledge for increased predictability and manufacturability. This intelligence includes hardware implementations for optimal yield in the design phase and extends to include test, repair, and diagnostics for manufacturability. Because Silicon Aware IP understands the behavior of silicon and is able to address post-silicon issues, it is key in helping designers maximize yield, increase test quality, increase reliability, speed time-to-volume, and improve overall manufacturability.

To help the systems designers address the challenges of the environment SoC core-to-interface, interface-to-package, and package-to-board and other SoCs including the impact on the system behavior and performance, the company introduced System Aware IP. The company’s System Aware IP offering, like the Intelli product line, is designed to mitigate any impact the environment may have on the overall system to ensure performance and functionality requirements are met.