Custom and analog design productivity has become a major issue at advanced process nodes, and PDK development and availability is a key bottleneck in new process technology adoption. The objectives of the collaboration are to reduce the time and effort needed for nanometer PDK development, to better optimize PDK devices for ultra-complex design rules, to facilitate creation of sophisticated devices such as spiral inductors and differential pairs, and to optimize run-time performance of PDK devices in system-on-chip (SoC) designs.
“Ciranova’s PyCell technology and advanced architecture provides native support of interoperable PDKs, which are an integral part of our Open Innovation Platform™, to facilitate and accelerate designers’ innovations in analog and full custom designs,” said Fu-Chieh Hsu, vice president of Design & Technology Platform at TSMC. “We are collaborating with Ciranova to develop the industry’s first interoperable PDK, a single PDK that supports multiple design environments. We continue to work with Ciranova and the interoperable PDK Library (IPL) Alliance to accelerate the deployment and adoption of interoperable PDK across the industry.”
“Every leading-edge SoC company in the world is under pressure to ramp more advanced design kits faster, despite limited time and resources,” said Eric Filseth, chief executive officer of Ciranova. “TSMC is the foundry gold standard, and we’re excited to be working with them to push the state of the art of PDKs forward.”
About PyCells:
Unlike older PCell approaches, the PyCell architecture is design-rule aware and generates DRC-correct device geometry automatically; the result is a major reduction in user coding effort, particularly at nanometer process nodes.
Ciranova is US-based electronic design automation (EDA) company.
