Sierra Monolithics, Inc. (Sierra Monolithics) has introduced a new 100G multiplexer (MUX) with clock multiplier unit (CMU) and demultiplexer (DEMUX) with clock and data recovery (CDR). The new Theta-100G solution incorporates SMI10021 10:4 MUX/CMU and SMI10031 4:10 CDR/DEMUX devices. Each uses the same fourth-generation, 130-nanometer IBM 8HP bipolar complementary metal-oxide semiconductor (BiCMOS) silicon germanium (SiGe) process technology, as the new 40G solutions.
The new Theta-100G solution allows low size, cost and power consumption. The new devices are key components for the equipment utilized in both the short-reach data center and the high-performance computing market, and also long-haul and metro carrier networks that carry growing volumes of IPTV, Internet video, multimedia conferencing, HD programming, mobile video phones, on-line gaming, networked storage and the other high-bandwidth transport payloads.
“Sierra Monolithics has built on the leadership foundation of our pioneering 40G family to deliver the industry’s first 100G MUX/CMU and CDR/DEMUX,” stated Javed Patel, president and chief executive officer of Sierra Monolithics. “This chipset will enable the development of 100G transponder modules and line cards that will relieve carriers’ increasingly congested network routes and significantly lower their transport costs per bit, while also increasing throughput in data center networks so they can support today’s exponentially growing demand for video, peer-to-peer and virtualization services.”
The new devices are available in a surface mount Ball Grid Array (BGA) package. BiCMOS is a natural choice for the 100G as it is well suited for the fast transistor switching needs where low noise is necessary. Bipolar SiGE results in high gain, high frequency, and the low noise floor as compared to the CMOS, enabling transmission systems to meet the stringent eye quality parameters. The new Theta-100G chipset operates at 4 x 25.0Gb/s to 28.3 Gb/s (100-113 Gb/s) and includes an integrated, dual-polarization quadrature phase-shift keying (DP-DQPSK) modulation precoder function that makes 100G networks extremely resistant to type of impairments that are frequently encountered in older fiber.
The industry is presently finalizing the standards for 100 Gbit/s data transmission, at the same time that the 40G networks are moving into general installment phase, initially in router interconnect applications. A single 100G wavelength offers ten times the bandwidth of new dense wavelength division multiplexing (DWDM) transport solutions, enough to support 800,000 simultaneous Internet calls. 100G standards are also anticipated to offer a convergence point between transport and Ethernet networks, by uniting WANs using SONET/SDH/OTN standards with LANs using Ethernet.
“After years of delay, network operators finally are moving on a wide scale to deploy 40-Gbit/s DWDM in their networks,” stated Sterling Perrin, senior analyst with Heavy Reading. “But even as 40G begins to take hold, carriers already are anticipating a migration to 100G. The market eagerly awaits new products from suppliers of 100G chips, components and systems that will make 100G technically and economically viable.”
Product Details:
The new Theta-100G chipset includes a 10×10.3Gb/s (MLD/CAUI) or 11×11.2Gb/s SFI-S interface on client side, and also a de-skew function in compliance with the OIF SFI.S, plus a line side pre-skew function for MLD/CAUI interface with a depth of 84UI. The addition of on-chip, selectable single- and dual-DQPSK precoding circuitry offers high spectral efficiency, high optical signal-to-noise ratio sensitivity, and robustness against dispersion. The DQPSK precoding function is implemented with the dual I/Q-interleaved outputs (4x28Gbps) for dual-polarized (DP-DQPSK) applications. The precoding function may also be configured to allow a single-pole 2x56Gb/s DQPSK modulation structure with a pair of external 2:1 multiplexers through use of synchronous high-speed clocks which may be programmed to any desired clock-to-data skew.
Other features incorporate on-chip selectable phase detector on-chip dual-mode (PRWS) pattern generators and the error checkers, and SPI control interfaces with the clock rates to at least 150 MHz. Typical jitter swing is 3.7psec p-p typical, and the differential output level is 0.6 to 1.2V p-p. The power consumption is a low 4 Watts max with the high-speed clock outputs disabled. The new chipset will allow the development of 100G-capable line cards and the transponders, and will support the 300-pin multisource agreement (MSA) pluggable module definition and, in the future, smaller form factors, as well.
The new Theta-100G SMI10021 and SMI10031 devices will sample in the second quarter of 2009, and scheduled to enter volume production in the fourth quarter 2009.
Sierra Monolithics, Inc. is a US-based supplier of high-performance ICs and modules.