The phase one of the AMBA 4 specification includes definition of an expanded family of AXI interconnect protocols including AXI4, AXI4-Lite and AXI4-Stream. The AXI4 protocol adds support for longer bursts and Quality of Service (QoS) signaling, and is a natural extension of the AMBA 3 specification, the company said.
In addition, long burst support aids integration of devices with large block transfers, and QoS signaling provides the ability to manage latency and bandwidth in complex multi-master systems.
According to the company, the AMBA 4 specification has been designed by and for the industry with contributions from 35 of the industry’s OEM, semiconductor and EDA vendors.
ARM added that the new AMBA 4 specification and the AXI4 protocols have also been extended to meet the needs of FPGA implementations. AXI4-Lite is a subset of the full AXI4 specification for simple control register interfaces, reducing SoC wiring congestion and simplifying implementation, while the AXI4-Stream protocol provides streaming interface for non-address-based, point-to-point communication, such as video and audio data.
Keith Clarke, vice president and general manager of fabric IP processor division at ARM, said: “These new specifications are a clear demonstration of the ongoing technical development and innovation in on-chip communication by ARM, and also the ongoing extension of the AMBA specification into new areas such as the FPGA community.
“Standards such as AMBA, which are widely adopted across the industry, enable significant benefits in design reuse, increased efficiency and interoperability which can be utilized by every level of the design community. The AMBA 4 specification will take embedded system design to performance and efficiency levels considered the exclusive domain of desktop, laptop and network equipment.”
Phase two of the new AMBA 4 specification will be issued later in 2010. The company said that these will include additional enhancements such as memory coherency and barriers support, which will simplify the software programmer’s view of the compute sub-system and reduce traffic to the external memory, further maximizing performance and power efficiency.
