The process has completed reliability testing at Samsung Foundry’s 300-millimeter logic fabrication line, the S Line, in Giheung, Korea and, is now ready for production of customer designs. Samsung Foundry will now begin volume manufacturing of chips designed to meet the energy-efficient requirements of mobile consumer electronics.
Leveraging its deep sub-micron knowledge in low power technology, Samsung Foundry, together with the IBM Joint Development Alliance (JDA), has tuned its 32nm LP HKMG gate process node to deliver a platform with double the logic density of 45nm processes through minimized restrictive design rules.
The company said that as part of the qualification process, it designed and manufactured a 32nm LP system-on-chip (SoC) that shows 30% power reduction and 55% leakage power reduction when compared to the SoC design implemented at 45nm LP at the same frequency.
In developing the 32nm LP process, Samsung Foundry worked in close engineering partnership with its ecosystem partners.
Samsung Foundry worked with EDA partners including Synopsys, Cadence Design Systems and Mentor to incorporate advances into the design flow for 32nm LP such as advanced low power techniques including power gating, multi-threshold voltages, multi-channel lengths and adaptive body biasing techniques were used to reduce leakage power.
Stephen Woo, executive vice president and general manager of system LSI at Samsung Electronics, said: “Collaborating with several key partners, we have been able to take HKMG from development to implementation in a production environment.
“Our customers can now seamlessly integrate their design innovations with the most advanced 32nm LP HKMG process technology, design tools, IP and manufacturing to accelerate time to market for their leading edge mobile silicon solutions.”
