The grouping of Talus Design with the Talus Vortex offers an entire RTL-to-GDSII solution for executing the advanced designs, allowing designers to fully optimize and precisely predict final chip performance early in design cycle and reduce design iterations.
Sigma Design, an early adopter of the Talus Design, has utilized the product in numerous recent high-performance tape-outs.
Managing, importing and exporting the various databases and files required for each tool in traditional flows is a complex, time-consuming task and can introduce errors into the design, stated Jacques Martinella, vice president of engineering of Sigma Design. With Magma’s RTL-to-GDSII flow, all the design data is captured in a single binary file called a Volcano(tm). This dramatically simplifies data management and improves our overall productivity. The tight integration of this system and the recent enhancements to Talus Design and Talus Vortex were key to Sigma’s decision to standardize on the Magma flow.
The technical challenges of nanometer design have been compounded by economic pressures to create more complex and differentiated chips in less time and with fewer engineering resources, stated Premal Buch, general manager of Magma’s Design Implementation Business Unit. By leveraging the same optimization and analysis engines available in the Talus Vortex physical design environment, Talus Design offers designers the high degree of predictability and improved productivity needed to meet tough performance and turnaround-time requirements.
Talus Design: Fast, High-Capacity RTL and DFT Synthesis:
Leveraging the high capacity of Magma’s unified data model and with enhanced memory efficiency over previous products, the new Talus Design synthesizes multimillion-instance RTL designs without the hierarchical partitioning or guard-band-related timing constraints. The capacity restrictions of the traditional tools need designers to break up large designs into many blocks and limit designer’s ability to optimize the design. Talus Design’s high capacity allows complete chips or just a few large blocks to be synthesized in a single pass and delivers superior optimization results. An incremental elaboration capability enables small changes to the design’s RTL to be propagated quickly into the implementation flow without the time-consuming and error-prone manual process of recompiling the complete design. Elaboration engine enhancements now offer concurrent language support for VHDL, Verilog and System Verilog.
To enhance testability of the design, the new Talus Design supports top-down and bottom-up hierarchical scan insertion all through the synthesis and physical design flow. The new Talus Design has a comprehensive and configurable DFT flow check engine that enables the user to analyze and debug testability issues. With these capabilities and proven interoperability with third-party test solutions, Talus Design offers comprehensive DFT support.
Talus Design and Talus Vortex: A Single Solution for Improved Predictability and Productivity:
The entire Magma Talus flow removes timing mismatches between the synthesis and physical design as it is built on a unified data model and utilizes a single static timing analyzer throughout the Talus RTL-to-GDSII flow. Talus Design allows logic designers to experiment at early stages of the design process with incomplete data to enhance RTL and timing constraints. These early optimizations eradicate time-consuming iterations toward the end of the design cycle and enable the logic designer to hand off the design to the implementation team with a very high degree of confidence that it will attain design closure.
Using a single Volcano database, the designers benefit from a complete self-documenting repository for all the design information, ensuring an error-free method of exchanging information between the logical and physical design teams. Magma Tcl scripting is also available all through the tool flow to assist automate and simplify complex tasks, delivering a powerful, productive environment that allows the designers to meet the technical and market challenges of semiconductor designs.
