Sigrity, Inc. (Sigrity) has introduced new advanced analysis solution, channel designer. It provides the flexibility and accuracy required for the high-speed serial links. Channel designer has many advanced features to help the designers at every stage from feasibility studies through design verification. The new product's net-based block-wise schematic editor supports rapid design capture for a single net interconnect or a complete bus traversing multiple boards.

Our customers have found that designs with high-speed serial links operating at multi-gigabit speeds require more than traditional analysis, said Jiayuan Fang, president of Sigrity. It is essential to accurately predict bit error rate to ensure a robust implementation that can handle anticipated jitter and noise levels. With millions of bits of data to be considered over a wide frequency spectrum from DC to tens of gigahertz, it can be extremely challenging to obtain reliable time-domain simulation results from band-limited channel models. Channel Designer provides unparalleled precision, and builds on the company’s long-standing strength in S-parameter handling for accurate system-level transient simulation.

The company’s model connection protocol (MCP) automatically connects circuit models for each element of the channel identified in the schematic. Channel templates of board, package and connector structures are provided. Detailed models extracted from physical layout user databases are swapped in as designs progress. Channel designer fully supports the IBIS Algorithmic Modeling Interface (AMI), which has emerged as the industry standard for transmitter and receiver modeling. AMI models now are available from leading IC vendors, and the company provides a number of useful generic AMI-compatible transmitter and receiver models for early assessments of IO behavior. The company’s unique support for cascaded AMI models simplifies model creation, testing and use.

Channel designer uses equalization and clock data recovery (CDR) modeling to anticipate the end-to-end behavior of serial links, and it rapidly simulates design alternatives. Advanced scenario sweep automation quickly identifies design boundaries.

Channel designer also includes automated crosstalk analysis that specifically targets crosstalk-induced jitter and noise arising in links operating at more than 10 gigabits per second. Designers can quickly assess crosstalk from any number of sources, anywhere along the channel. The channel analysis output includes 2D and 3D eye diagrams, along with bathtub curves, for accurate bit error rate prediction.