HiSilicon has expanded its use of the Cadence Encounter Digital Implementation System, Encounter Power System and Virtuoso custom design technologies in its low-power and mixed-signal flows at advanced technology nodes.
HiSilicon has also adopted the Cadence Encounter Conformal ECO Designer in its engineering-change-order flow to help designers reduce both cost and impact on schedules resulting from late iterations.
Adopting the Cadence technologies enables HiSilicon to improve the productivity of its engineering groups in implementing low-power designs, the company said.
The Cadence Encounter Digital Implementation System, with its technology and low-power support for multiple power domain designs, allows HiSilicon to leverage power-saving techniques, such as power shutoff and voltage scaling, according to the company.
The mixed-signal capabilities within the Cadence Virtuoso custom design technologies and the Encounter Digital Implementation System allow HiSilicon’s analog and digital design teams to collaborate by making digital implementation capabilities accessible from within the custom design environment, and vice versa.
With these capabilities, as well-mixed signal and low-power signoff, the Encounter Digital Implementation System provides HiSilicon with a complete implementation and signoff system for mixed-signal and low-power designs.
Teresa He, vice president of HiSilicon, said: “After careful evaluation, we have chosen Cadence as the primary vendor of our low-power and mixed-signal design flows.
”Today’s global semiconductor market is highly competitive and we are happy to sharpen the saw with the leading technologies from Cadence.”
