Sharp said the Palladium technology shortened overall verification time while helping boost product quality through rapid bring-up of its system verification environment and integrated debugging flow.

By deploying the Palladium technology, Sharp eliminated the need to design and produce breadboards, as well as engineering efforts required to partition designs into several FPGA units. Bring-up of verification interfaces was simplified through the use of Cadence SpeedBridge® Adapters for leading-edge protocols. Deploying the Palladium Incisive compiler also helped save Sharp time and ensure quality.

Furthermore, Sharp leveraged the Palladium III product’s FullVision debugging feature, which provides full visibility in identifying the bugs in hardware and/or software. Advanced verification techniques, such as assertions, are also supported in the Palladium verification environment, which can greatly improve product quality and traceability. These features provide Sharp verification teams the required verification throughputs and ease of use while minimizing the effort needed to debug the design in a system-level environment.

Our major goal is the enhancement of customer satisfaction by meeting or exceeding applicable industry standards for quality and reliability, said Hiroshi Kubo, division deputy general manager of the System Device Division at Sharp. The Palladium system enabled our new methodology while making it easier and faster to build a verification environment than with our traditional system validation with breadboards, which we mainly used in the past. The Palladium system has helped to improve our system design quality, and we plan to deploy this system-level verification solution to new projects. Ultimately it will increase overall product quality with shorter verification time and less development cost.

With the Palladium environment, engineers can start software development months earlier in the design cycle by collaborating with the hardware development team before the actual hardware descriptions are finalized or made available in silicon. This enables Sharp’s teams to find and eliminate critical bugs that may exist at the system level, as well as those on hardware or software.

The Palladium series of accelerator/emulators from Cadence is the market segment leader for system-level verification, and for good reason, said Christopher Tice, senior vice president and general manager of system design and verification at Cadence. Sharp’s experience and success using the Palladium III series highlights our ability to provide overall project-level value for system development worldwide.