Cadence Design Systems, Inc. (Cadence), a US-based developer of electronic design automation (EDA) software and hardware, has introduced new Si2 Common Power Format (CPF) version 1.1 of Low-Power Solution to support new on-chip power management schemes. The new solution spans the Cadence Encounter digital implementation and logic design technologies, as well as the Incisive functional verification and system design and verification technologies.
This solution enables designers to more accurately model, analyze and debug power management components targeted for integration into large system-on-chip (SoC) designs. The CPF Version 1.1 includes macro modeling, seamless multi-language support for IP integration and automated support of metric-driven verification methodologies, such as those in the new Cadence Incisive Enterprise Simulation Environment.
The power macro-modeling capability allows more accurate characterization and analysis of power consumption within complex SoC IP. The Cadence Low-Power Solution is also completely generalized to enable a multitude of popular programming approaches to IP block integration, and delivers automated low-power design capabilities that extend well beyond implementation. These enhancements enable the IP block or SoC to operate as designed and within the power parameters required by the end application.
Virage Logic is one proponent of the improved CPF-enabled. Virage Logic is a provider of advanced technology solutions and has broadened the power management capabilities of its SiWare Memory and SiWare Logic product lines. By utilizing these products with the Cadence Low-Power Solution, SoC designers can more accurately analyze the benefits of the power management schemes in the context of their full designs.
As the semiconductor industry’s trusted IP partner, we recognize that support for macro modeling is essential for accurate power modeling in today’s complex memory sub-systems, said Brani Buric, executive vice president of marketing and sales at Virage Logic. Our support of the Cadence Low-Power Solution enables us to deliver accurate power modeling to our mutual customers, which in turn enables them to develop complex, multifaceted SoCs that are fully capable of optimizing the low-power capabilities embedded in each IP block.
Another user of the CPF-enabled Cadence Low-Power Solution is Sonics, a leading provider of intelligent interconnect solutions that manage the on-chip communications in system-on-chip devices. Sonics provides our customers with low-power on-chip connectivity solutions that allow a high degree of power control, said Jack Browne, senior vice president of marketing and sales at Sonics. The inclusion of CPF 1.1 in Sonics products is an efficient way for designers to leverage these low-power solutions as designers integrate the IP back into their design flow.
Through the metric-driven Cadence Incisive Enterprise Simulation suite, the Cadence Low-Power Solution now enables automated assertion generation and automated low-power coverage for low-power intent verification; voltage-aware simulation and voltage tracking; full multi-language support for low-power verification; and powerful new debug and visualization mechanisms.
As customers innovate and create new methods to achieve more power-efficient IC solutions, we are driven to innovate alongside them, said Steve Carlson, vice president of Low-Power Solutions at Cadence. It is tremendously gratifying to work so closely with the broad ecosystem of customers and collaborators to deploy these solutions quickly into the design community.