Cadence Design Systems, Inc. (Cadence) has introduced new FPGA-synthesized C-to-Silicon Compiler for Altera and Xilinx FPGAs. The new compiler is a flagship electronic system-level (ESL) technology for hardware design and implementation. C-to-Silicon Compiler enhances designer productivity up to 10 times in creating and re-using system-on-chip (SoC) IP. This compiler is focused on ASICs and delivers the same output benefits to SoC IP blocks designers targeting Altera and Xilinx FPGAs.
We are starting to use C-to-Silicon Compiler in several production ASIC designs, and are recommending it to the other Hitachi design groups, said Toru Hiyama, general manager, MONOZUKURI Innovation Operation, Hardware MONOZUKURI Division at Hitachi, Ltd. We requested Cadence for FPGA synthesis support earlier last year, expecting more designers would use C-to-Silicon Compiler not only for ASIC designs but also for high-priority FPGA designs. We are very pleased to see FPGA support capability available on C-to-Silicon Compiler, and the quality of results using C-to-Silicon Compiler is very promising.
The C-to-Silicon Compiler was launched in July 2008 with two unique capabilities in high-level synthesis, Embedded Logic Synthesis (ELS) and a Behavior Structure Timing (BST) database. ELS use Cadence Encounter RTL Compiler global synthesis to help ensure high accuracy and high-quality implementation results. The BST database enables design teams to perform true incremental synthesis, for example, re-synthesizing only the parts of the design that changed while leaving the rest of the design untouched. The latest release of the C-to-Silicon Compiler extends these capabilities from ASICs to FPGAs, with the same benefits.
The C-to-Silicon Compiler very effectively handles mixed control/datapath designs, as well as incremental synthesis, said Steve Svoboda, product marketing director at Cadence. In response to several customer requests this year, we applied our unique ELS technology to designs targeting the Altera and Xilinx FPGA families like we did with Cadence RTL Compiler. As a result, customers now get the same advantages with high-level synthesis whether they are targeting their designs to FPGAs or to ASICs.
As FPGAs perform more functions within systems, there is an increasing level of interest among our customers for technologies that help reduce development times, said Chris Balough, senior director of software, embedded, and DSP marketing at Altera. Cadence’s C-to-Silicon Compiler provides an innovative approach to high-level synthesis that helps FPGA designers increase their productivity and quality of results.
With the capacity and performance of Xilinx’s Virtex-5 and Spartan-3 FPGAs, design teams are searching for high productivity and faster time to market, said Tom Feist, senior director of ISE Design Suite at Xilinx. C-to-Silicon Compiler and its integration with Xilinx Synthesis Technology (XST) is a great start toward achieving this goal, raising the level of abstraction and design exploration above what can be found in traditional HDL flows. By expanding our collaboration with Cadence, we strive to meet the demand of our mutual customers for enhanced productivity and higher quality of results.
The Cadence C-to-Silicon Compiler is available in limited production, and is designed to work with the Altera’s Quartus II software and Xilinx Synthesis Technology FPGA-synthesis tools available from Altera and Xilinx, respectively. Its capabilities will be demonstrated in the Cadence booth during the Electronic Design and Solution Fair (EDSF) January 22, 2009 to January 23, 2009 in Yokohama, Japan.