This approach facilitates propagation of design efficiencies to detailed, back-end implementation with minimized schedule risk.

Atrenta’s SpyGlass-CDC product analyzes System-on-Chip (SoC) designs to ensure complex clock synchronization schemes, such as FIFOs and handshakes, are correct. Bugs in faulty clock domain synchronizations between IP blocks in a chip are hard to find with conventional design tools and represent a leading cause of chip re-spins and field reliability issues.

The Atrenta SpyGlass-CDC product provides detailed clock domain synchronization checking, useful for external IP and IP integration verification, said Rick Bahr, vice president of engineering for Atheros. We are pleased to adopt this EDA tool to assist us with product development efficiencies.

The ever-increasing use of third party semiconductor IP is creating a growing need for rigorous validation of clocking schemes, said Mike Gianfagna, vice president of marketing at Atrenta. Our SpyGlass-CDC product is very effective at finding these hidden chip killers early in the process. We’re delighted that Atheros has chosen SpyGlass to assist with their leading edge designs.