More heavily populated grids meeting increasing electricity demand are putting an impossible strain on protective devices, leading to burned out circuit breakers, overloaded lines and an increased risk of cascading. The US electricity industry and the DoE are developing two very different technologies to help meet the challenge – a solid state current limiter to protect components at distribution voltage levels, and a superconductor-based fault current limiter to operate on the transmission grid.


Utilities protect their equipment against potentially disastrous power line shorts and other problems with circuit breakers, current limiting reactors and high-impedance transformers. When delivery networks are upgraded or new generation is added, fault levels can potentially increase beyond the capabilities of the existing protective equipment, placing circuit breakers in an “over-duty” condition. and necessitating upgrades of substations or wholesale replacement of circuit breakers. The problem is more severe at transmission level voltages where conventional solutions cost too much or are simply not available, but a new technology based on superconducting materials, known as MFCL, promises to correct this situation.

Advanced current interruption technology, using high power solid-state components, is a second technology being developed to meet current needs, and it has opened the door to high power control at a lower cost than ever before. By providing sub-cycle current limiting, the solid state current limiter alleviates the short-circuit condition in both downstream and upstream devices by limiting fault currents coming from the sources of high short-circuit capacity. Added functions, and strategic benefits that a conventional circuit breaker cannot offer, help to justify the higher cost associated with a device that is expected to offer a powerful new tool to utility engineers faced with the challenges of integrating new generation into existing power systems, clearing faults more quickly, or finding an alternative to SF6 breakers.

Much is claimed for the fault current limiters described here. Perhaps the greatest challenge for their makers is to accomplish their promise at a price that utilities can accept.


Electric utilities have long wanted a practical, reasonably priced, solid-state circuit breaker that could provide reliable service with little maintenance. The circuit breakers being developed by Electric Power Research Institute are claimed to meet this demand – they can time their closing to minimise transients, while a current limiting function significantly enhances the effectiveness of the device.

Limiting the current achieves fault isolation and better network protection, taking care of most of the distribution system situations that result in voltage sags. The SSCL therefore should substantially improve power quality by limiting fault current and controlling inrush current. High fault currents are known to be a factor in reducing transformer life; consequently, it is expected that an advantage for SSCL use will be longer equipment life with higher reliability for nearby transformers. The ‘instant’ response of solid-state power components makes it possible to produce a device that begins limiting fault current even before the first peak is reached. In a complementary effort, EPRI is funding work on advanced semiconductor materials. The semiconductor being used for the SSCL is SiC.

To date EPRI has made and tested silicon carbide GTOs capable of blocking 7200 V and that turned on and off with record speed. Operation was possible above 250°C. The size of SiC test devices remains small because the crystal material from which they are made contains so many defects that it is not practical to try large devices. However efforts are underway to improve the SiC crystal, and EPRI reports that the work is starting to show good results.

The benefit to utilities

Initially. SSCL options will be for distribution voltages. After SSCL is installed, existing circuit breakers can continue in service despite nearby new generation if the new generation is connected through an SSCL. Capacitor banks can be switched, with reduced transients in current and voltage. The SSCL can be operated frequently for switching without significant mechanical wearout.

When SiC devices are available in high power ratings, cost and size improvements should take place. Moreover savings in auxiliary circuits that control, monitor, and protect the central components can be expected to be substantial. Equipment will be dramatically smaller because of fewer components, resulting in lower losses. Reliability and maintenance costs are also expected to improve because of the smaller number of parts and simpler cooling.

How it works

To limit the current, the SSCL must rapidly insert an energy absorbing resistor into the circuit. Figure 1 shows some traces that have recorded this process. Note that the current switches from the normal path to the resistive path in less than a millisecond. In addition to limiting the fault current, the SSCL can also control the inrush current, even for capacitive loads, by gradually phasing in the switching device.

Other advantages:

• Repeated operations with high reliability and without wearing out the switch

• Reduced switching surges

• Avoided environmental problems of SF6.

It is expected that the SSCL will also offer an alternative, for a few key locations, to large scale breaker uprate programmes for power systems: and many other benefits including the avoidance of bracing problems with switchgear and the associated need for multibreaker outages, more rapid fault current solution deployment to mitigate the more uncertain and dynamic system planning process driven by independent power producers, avoidance of the diminishing effectiveness of traditional series reactor fault current solutions, a new tool to more effectively deal with pressures to add new transmission capacity, provide open access for distributed and aggregate generation, and deal with new fault current sources from emerging energy storage technologies.

Hardware development

The first phase of hardware development had the goal of producing a circuit module capable of the currents needed, but not the full voltage. Examples of this circuit have been made and successfully tested on a single phase basis. A single phase prototype has been made and tested for voltage withstand qualities in partial discharge, AC, DC, impulse, and chopped wave forms. Figure 2 shows this unit assembled. When EPRI has confidence in all of the operational functions of this single phase prototype, construction will proceed on a three phase, medium voltage prototype, which will undergo strenuous laboratory testing. Prototypes will then be made and sent for field trials, trials for which EPRI is currently seeking hosts.

After the test period, host utilities will be asked to report and comment on the performance of their units. EPRI’s contractor will make a commercial version of this device available to utilities. The final phase will be the development of higher voltage SSCLs, leading to a 138 kV SSCL. Because the electronic modules are simply stacked higher for increasing voltage, this work will benefit from and build upon the earlier phases. There is wide industry experience in constructing and operating large arrays of similar power electronics devices for ac to dc converters and for FACTS devices as high as 600 kV, so problems are not foreseen in this area.

SiC crystal research

SiC has an electronic structure that allows it to support higher voltage gradients and to operate at higher temperatures than silicon. Another bonus is that it has a thermal conductivity three times higher than silicon – slightly better than copper. Because of these properties, SiC has the potential to provide devices with three times the voltage limit of silicon and with twice the current density.

Wide band gap semiconductor materials are expected to replace silicon for high power switches in the future, leading to simpler, smaller, lower cost, more rugged powerhandling devices. The band gap energy is equivalent to the ionisation energy that can turn an insulating gas into a conducting plasma. Semiconductor band gaps are normally in the range from 0.7 to 5 eV.

Silicon has a band gap of about 1 eV, and the materials that have been classified as wide band gap materials have a value of about 2 to 5 eV. The effect of this band gap on electronic properties is not linear but is typically exponential, so this difference is significant. Although laboratory work is underway on several wide band gap materials, SiC is the most promising for medium term applications.

SiC crystal quality is now improving rapidly because of EPRI and US government funding of R&D. An SiC thyristor rated 8 kV and an SiC gate turnoff thyristor (GTO) rated 7 kV have already been operated, and it is expected that devices above 12 kV will be made within a few years. SiC devices are expected to have overwhelmingly better performance in circuits requiring more than 10 kV.

The quality of available SiC crystals has been a central issue for many years. The diameter of available wafers has grown from 25 to 50 mm and now to 75 mm, which is progress at a reasonable pace.

Efforts to reduce the defect density are not going so well. But projecting the present rate of progress makes it clear that SiC devices with high current ratings in areas of a square cm or larger will be commercially possible within a few years.

Dislocation densities have decreased significantly, but they still increase losses during power conduction.

Dislocations also serve as preferential sites for holes and electrons to recombine, so a high dislocation density is associated with a shorter lifetime of charge carriers. Lowering the lifetime of charge carriers makes a device faster responding, but it also increases the conduction loss in a device.

Over the years, the growth of silicon crystals has been improved to the point that dislocation densities are quite small, and the specification of allowable dislocation density is now a secondary concern. SiC crystals have not yet reached this level of quality.

Two kinds of defects have been the focus of development, namely dislocations and what are known as ‘micropipes’.

Dis are crystal imperfections at the atomic level consisting of lines along which the atoms of the crystal lattice do not properly align. They

Dislocations add to the resistance of a crystal and increase operating losses. However significant progress has been made, and this trend is expected to continue for the next few years.

Micropipes are dislocations on an atomic scale that in sufficient density render a device completely useless.

SuperPower HTS fault current limiter

A device designed to improve the control of and reaction to overcurrent at key points on transmission grids, and therefore reduce the likelihood of damage to grid components, and in extreme cases, cascading, is being developed by a joint project of Intermagnetics Corp, EPRI and the US Department of Energy. Projected HTS devices include transmission cables, fault current controllers and transformers. Intermagnetics subsidiary SupeerPower and its industry and government partners has developed working prototypes of these devices.

The DoE named Intermagnetics subsidiary SuperPower to lead the project, which is being undertaken as part of the department’s Superconductivity Partnership Initiative. EPRI had previously committed $600 000 toward the project, known as the matrix fault current limiter, which is scheduled for completion in 2006. Last year Intermagnetics Corp received a grant from the US DoE of half the projected $12 million cost.


To avoid the expensive upgrades necessary when power delivery networks are upgraded or new generation is added, a fault current limiter (FCL) can be applied to reduce the available fault current to a lower, safer level where the existing switchgear can still protect the grid. FCLs employing high temperature superconductors (HTS) provide the necessary current limiting impedance during a fault condition, but have essentially zero impedance during normal grid operation. Therefore, HTS FCLs have no negative impact on overall system performance, in contrast to conventional current limiting devices. A current limiting reactor for example produces large voltage drops, circulating currents in transformers and substantial energy loss. Numerous utilities have expressed the need for a device that can economically address breaker over-duty problems in an over-stressed transmission network. In response to this market pull SuperPower in conjunction with Nexans has developed the matrix fault current limiter which SuperPower say provides a more economical solution than many currently available to breaker over-duty problems.

SuperPower expects to receive patents on its MFCL design and plans to develop additional patentable technology during the programme.

MFCL will employ Nexans’ melt cast superconductors, as opposed to the more commonly employed wires or tapes, because of the substantially greater current carrying capacity required. It is anticipated that that melt cast materials, when combined with proprietary ‘Matrix’ technology, will yield a fault current limiter capable of withstanding burnout risks that could occur at transmission level currents. The MFCL technology is expected to limit fault currents within fractions of a second, with the capability to automatically reset and very rapidly prepare for successive surges.

Development programme

SuperPower’s “Matrix” technology allows scaling up to transmission voltage levels of 138kV. Individual modules contain HTS elements and an inductor connected in parallel that carries the current during the fault. The HTS elements consist of bulk BSCCO-2212 material, and are fabricated using Nexans’ melt-cast process. A number of these modules are arranged in an ‘mxn’ array to form the current limiting matrix. The programme includes the fabrication of three prototypes, a proof-of-concept pre-prototype, the Alpha prototype, and the Beta prototype, each with progressively higher ratings to scale up to the transmission voltage level. The Beta prototype will be designed to meet a specific utility application and will be installed on a 138kV transmission grid for demonstration in 2006.

The technology

In the superconducting state an electrical conductor exhibits no electrical resistance if the current flow through the material is below a certain threshold (the “critical current level” Ic), when operating below certain temperature and external magnetic field (the so called “critical temperature” Tc and “critical field” Hc) conditions. The superconductor shows no electrical resistance when the current is below the critical current level. If the current exceeds this level, the superconductor will undergo a transition from its super-conducting state to a resistive state, a transition termed “quenching”. As long as the heat generated (I2R loss) during the resistive stage does not damage the superconductor, it can be brought back to its superconducting state if sufficient cooling is provided to dissipate the heat quickly, lowering the temperature of the superconductor to within its critical range. Quenching, and subsequent recovery to a superconducting state, corresponds to a “variable resistance” effect. A superconducting device with such characteristics is ideal for current limiting applications. The MFCL is designed to use these characteristics to provide fast quench and first peak current limiting. A simplified explanation is depicted in Figure 5 where the MFCL is represented by the fault current limiting impedance. The HTS elements are represented by the variable resistance symbol and the parallel connected inductor represents the impedance built into the MFCL. Under the normal operating condition, the peaks of AC current flows through the superconducting elements will be below the critical current level of the superconductors – the MFCL will be in a superconducting state. Therefore, no major I2R losses or voltage drop will be developed across the device and it is basically “invisible” to the grid. Under the fault conditions however, the current in the grid exceeds by a large margin the critical current level. This surge current then forces the superconductor to transition from its normal state to a highly resistive state.

Once the superconductor is quenched, most of the current is diverted to the parallel connected inductor which provides most of the current limiting impedance during a fault. Once the fault is cleared, the HTS elements will cool and return to the superconducting state.

The HTS elements and inductors are arranged so that the device is modular and scalable and can be tailored to a range of applications. Each module consists of the HTS elements and an inductor connected in parallel. Figure 6 shows a simplified schematic of the concept, a variable resistor symbol representing the basic current limiting module. A number of these modules are then arranged in an mxn matrix to form the current limiter. The current level of the grid where the MFCL is connected determines the number of rows of the matrix, and the required current limiting impedance determines the number of columns.


A major benefit of MFCL is that it is passive. Detection of fault and insertion of current limiting impedance requires no active monitoring and control mechanism. Further, it places no substantial I2R loss or voltage drop burden on the system. In more practical terms its matrix configuration renders it modular and scalable, and there is an environmental benefit –no flammable or environmentally hazardous oil, and no SF6, are used.


The first of the three hardware prototypes, the single phase proof-of-concept pre-prototype, has been built and tested. It is rated at 8.6kV line to ground, 800 Arms continuous current and prospective faults of 25kA asymmetrical first peak. Its main internal components, the matrix of HTS elements and parallel-connected inductors, is contained in the matrix assembly immersed in a liquid nitrogen bath within the cryostat. The cryostat consists of an inner pressure vessel and outer vacuum vessel. Heat is removed from the bath with two cryocoolers. The external connection is made to the matrix through a set of lead assemblies.

A series of short circuit tests on the proof-of-concept pre-prototype has been performed at KEMA Power Test in Pennsylvania to demonstrate short circuit performance up to the rated levels. Figure 7 shows the current limiting results with for a prospective asymmetrical fault current of 25kA peak at 8.6kV line to neutral voltage. The black curve is the unlimited fault without MFCL in the circuit and the red line is the limited current with the MFCL in the circuit. When tested with the MFCL, the fault is applied for 3 cycles before the circuit breaker opens. This is typical of most of the tests results, with first peak current limiting and fast quench of the HTS elements. When expressed as the ratio of the limited to the unlimited current, the first peak limiting is 84% and the limiting achieved by the third cycle is 56%.

The next step is to scale the concept to high voltage, and develop the Alpha prototype. This stage of the development programme will focus on the technical challenges of operating an HTS device at high voltage. The eventual object is to create a 400 kV unit, but this aim has not yet taken the form of a schedule.