Silicon Clocks, Inc. (Silicon Clocks) has introduced new high-performance, configurable J-series precision frequency synthesizers. The J-series products are based on the company’s SmartPLL technology platform. They exhibit lower jitter over a broad range of temperatures and supply voltages at less cost and power consumption relative to competing solutions. The J-series synthesizer family has two devices, featuring a single precision clock output in LVPECL at differing output frequencies.
The J-Series products support most of high-speed serial communications standards, including: Ethernet, 10G, 12G, XAUI, SATA, FibreChannel, SDH SONET, PCI-e, and SRIO.
The J-Series is an attractive alternative for the markets traditionally served by a number of expensive, bulky, high-power, solutions requiring expensive crystal or SAW components. The J-Series gives SONET-level performance at a price point, flexibility, power, and form factor that makes it attractive for the cost-constrained, high-volume applications.
Additional products will be added in a while with different I/O types (LVDS) based upon necessary output frequencies. Full industrial temperature range compliance (-40 ºC to +85 ºC) over both 3.3 V and 2.5 V ranges, coupled with a very low noise and the low power design, yield accuracies of less than 1 ps rms jitter (600 fs is typical) and result in the very low phase noise between 12 kHz and 20 MHz. The company’s SmartPLL architecture exhibits a ±0 ppm periodic error contribution for PLL, thus offering an extremely stable output frequency with excellent duty cycle (48/52 worst case) and very low dynamic power consumption (<80 mA).
The outputs are robust with the fast edges (<500 ps), and are capable of driving one or two transmission lines, offering a precision clock output that can be configured for the one of 23 supported frequencies ranging from 62.5 MHz up to 670 MHz. The J-Series products are available in the wafer form, tested dice or packaged in a small form factor 3 × 3 mm QFN. A fully integrated crystal oscillator circuit, complete with internal trim/loading caps, yields a low device count, while the configuration pins enable for setting the output frequency.
“We have worked toward a best-in-class CMOS implementation for a configurable Frequency Synthesizer that can address a wide range of High Speed Serial Data (HSSD) standards,” said Silicon Clocks chief executive officer Didier Lacroix. “Our SmartPLL™ technology platform yields high-performance VCOs and PLLs, providing our customers with precision timing solutions that meet and exceed expectations for cost, performance and accuracy. As a developer of custom timing solutions, focused on new product development, we worked closely with our partners to ensure that our products have a real market appeal and are actively sold through their existing sales channels.”
Mark Sherwood, principal associate at CS &A LLC, a market analyst and consultant focused on the Semiconductor Timing, said: “The J-series™ has achieved and demonstrated high stability and excellent accuracy making it competitive for Physical Layer and MAC timing solutions – Host Bus adapters, Network Interface Cards, Access Points, Routers, Switches, Hubs and more can benefit from the ultra low noise, low power, and small form factor. This family of products is competitive with solutions from IDT, Maxim, Analog Devices, and provides for a path to lower cost, high performance XO solutions.”